Re: [PATCH 11/14] clk: renesas: Add r8a774e1 CPG Core Clock Definitions

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

On Tue, Jul 7, 2020 at 6:18 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> wrote:
>
> From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@xxxxxxxxxxxxxx>
>
> Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in
> Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's
> Manual.
>
> Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@xxxxxxxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in clk-renesas for v5.9, in a branch shared by driver
and DT (renesas-r8a774e1-dt-binding-defs).

> --- /dev/null
> +++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h

> +#define R8A774E1_CLK_CANFD             46

I guess it's fine we keep CANFD last, for consistency with other RZ/G2
SoCs (CANFD was not present in early revisions of the Hardware User's
Manual).

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

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