[PATCH v1 2/2] gpio: merrifield: Better show how GPIO and IRQ bases are derived from hardware

[Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>]

It's a bit hard to realize what the BAR1 is for and what is the layout
of the data in it. Be slightly more verbose to better show how GPIO and
IRQ bases are derived from the hardware.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
---
 drivers/gpio/gpio-merrifield.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c
index 1f0cf909ea40..cdd782a186aa 100644
--- a/drivers/gpio/gpio-merrifield.c
+++ b/drivers/gpio/gpio-merrifield.c
@@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id
 
 	base = pcim_iomap_table(pdev)[1];
 
-	irq_base = readl(base);
-	gpio_base = readl(sizeof(u32) + base);
+	irq_base = readl(base + 0 * sizeof(u32));
+	gpio_base = readl(base + 1 * sizeof(u32));
 
 	/* Release the IO mapping, since we already get the info from BAR1 */
 	pcim_iounmap_regions(pdev, BIT(1));
-- 
2.25.1