On Wed, Nov 13, 2019 at 10:54:36AM +0100, Linus Walleij wrote: > On Wed, Nov 6, 2019 at 3:48 PM Andy Shevchenko > <andriy.shevchenko@xxxxxxxxxxxxxxx> wrote: > > > Intel Lynxpoint GPIO is actually half way to the Chassis specification that has > > been established starting from Intel Skylake. It has some pin control > > properties we may utilize. To achieve this, move the driver under pin control > > umbrella and do a bunch of clean ups. > > > > This is the first step. Next step will be to convert it to the actual pin > > control driver. > > > > The series has been tested on Harrisbeach Ultrabook where Lynxpoint GPIO is > > exposed to the OS. > > > > Andy Shevchenko (8): > > pinctrl: lynxpoint: Move GPIO driver to pin controller folder > > pinctrl: lynxpoint: Use raw_spinlock for locking > > pinctrl: lynxpoint: Correct amount of pins > > pinctrl: lynxpoint: Keep pointer to struct device instead of its > > container > > pinctrl: lynxpoint: Use %pR to print IO resource > > pinctrl: lynxpoint: Switch to memory mapped IO accessors > > pinctrl: lynxpoint: Convert unsigned to unsigned int > > pinctrl: lynxpoint: Move ->remove closer to ->probe() > > I'm a big fan of this refactoring. Glad we are on the same page about it! > Can you send this series as a separate pull request that I can pull into > the GPIO tree rather than pin control, or maybe both, once you're > pleased with it? I have done more and it still requires some work. I will send v2 after merge window being closed. -- With Best Regards, Andy Shevchenko