On 2019-11-12 13:21, Yash Shah wrote:
Adds the GPIO driver for SiFive RISC-V SoCs.
Signed-off-by: Wesley W. Terpstra <wesley@xxxxxxxxxx>
[Atish: Various fixes and code cleanup]
Signed-off-by: Atish Patra <atish.patra@xxxxxxx>
Signed-off-by: Yash Shah <yash.shah@xxxxxxxxxx>
[...]
+static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
+ unsigned int child,
+ unsigned int child_type,
+ unsigned int *parent,
+ unsigned int *parent_type)
+{
+ /* All these interrupts are level high in the CPU */
+ *parent_type = IRQ_TYPE_LEVEL_HIGH;
It is bizare that you enforce LEVEL_HIGH here, while setting it to NONE
in the PLIC driver. These things should be consistent.
+ *parent = child + 7;
Irk, magic numbers...
M.
--
Jazz is not dead. It just smells funny...
