This GPIO controller is present on a number of Broadcom switch ASICs with integrated SoCs. It is similar to the nsp-gpio and iproc-gpio blocks but different enough to require a separate driver. Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx> --- Notes: Changes in v2: - Document as DT schema - Include ngpios, #gpio-cells and gpio-controller properties .../bindings/gpio/brcm,xgs-iproc.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.yaml diff --git a/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.yaml b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.yaml new file mode 100644 index 000000000000..71998551209e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/brcm,xgs-iproc.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/brcm,xgs-iproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom XGS iProc GPIO controller + +maintainers: + - Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx> + +description: | + This controller is the Chip Common A GPIO present on a number of Broadcom + switch ASICs with integrated SoCs. + +properties: + compatible: + enum: + - brcm,iproc-gpio-cca + + reg: + minItems: 2 + maxItems: 2 + description: + The first region defines the base I/O address containing + the GPIO controller registers. The second region defines + the I/O address containing the Chip Common A interrupt + registers. + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 32 + + interrupt-controller: + type: boolean + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +allOf: + - if: + properties: + interrupt-controller: + contains: + const: true + then: + required: + - interrupts + - '#interrupt-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpio@18000060 { + compatible = "brcm,iproc-gpio-cca"; + #gpio-cells = <2>; + reg = <0x18000060 0x50>, + <0x18000000 0x50>; + ngpios = <12>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + }; + + +... -- 2.23.0