RFC: generalizing gpio register set types

["Enrico Weigelt, metux IT consult" <lkml@xxxxxxxxx>]

Hi folks,


I'm curious about what types register sets the various gpio controllers
have, in order to find out whether there's still room for a bit more
generalization. Hopefully I'd like to find some formal description of
(most) gpio controllers, so we could do many drivers pretty much in
a declarative way. (eg. by just filling some structs)

For example, the AMD FCH's gpio controller has one 32bit register per
line, which includes control and data flags. The actual register banks
don't seem to be linear, but that might be an misinterpretation of the
rare information i've got - perhaps certain gpios are just used
internally for not aren't wired.

This is an example of an what I'd like to call "one-reg-per-line" class.
The controller/device specific attributes here are:
  * control register width (eg. 32bit)
  * direction flag: bit# / mask, polarity
  * io/data flag: bit# / mask, polarity
  * map of gpio names/logical IDs <=> registers (relative to offset)
When generalizing probe/setup code, also:
  * register base address
  * oftree / acpi match tables
  * device name

I'm planning to write a generic driver, if we have more consumers for
that and solve the problem of generic passing of platform configuration
data, w/o using driver specific pdata structs.

There's another class, which we IMHO have a generalization for, is those
devices that have one wide register for all direction and one for all
data flags.

Does anybody know other classes that I didn't mention here ?


--mtx

-- 
Enrico Weigelt, metux IT consult
Free software and Linux embedded engineering
info@xxxxxxxxx -- +49-151-27565287