Re: [PATCH v3 6/6] ARM: PWM: add allwinner sun8i R40/T3/V40 PWM support.

[Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>]

Hello,

On Mon, Nov 26, 2018 at 10:31:58PM +0100, Uwe Kleine-König wrote:
> > +static int sun8i_pwm_config(struct sun8i_pwm_chip *sun8i_pwm, u8 ch,
> > +			    struct pwm_state *state)
> > +{
> > +[...]
> > +		clk_rate = clk_get_rate(clk);
> > +		val = state->period * clk_rate;
> > +		do_div(val, NSEC_PER_SEC);
> > +		if (val <= 1) {
> > +			dev_err(sun8i_pwm->chip.dev,
> > +				"Period expects a larger value\n");
> > +			return -EINVAL;
> > +		}
> > +
> > +		/* change clock source to "mux-1" */
> > +		clk_disable_unprepare(sun8i_pwm->clk);
> > +		devm_clk_put(sun8i_pwm->chip.dev, sun8i_pwm->clk);
> > +		sun8i_pwm->clk = clk;
> 
> sun8i_pwm is shared for all 8 PWMs, right? So if you assign mux-1 here
> for the second mux, how does this influence the first PWM?

To clearify my question:

after the first pwm is used and enabled (maybe using mux-0) changing
sun8i_pwm->clk for the second pwm is broken because then when the first
pwm is disabled the wrong clock is stopped.

Best regards
Uwe

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Pengutronix e.K.                           | Uwe Kleine-König            |
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