tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git gpio-descriptors-regulator-fixup head: efc08549a219debb5c641739ca0f01af97fd0f64 commit: fbc2a5f2f68f0a0f8bdac6880849d9a112c29184 [10/11] regulator: s5m8767: Let core handle GPIO descriptors config: x86_64-randconfig-x012-201847 (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: git checkout fbc2a5f2f68f0a0f8bdac6880849d9a112c29184 # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers//regulator/s5m8767.c: In function 's5m8767_pmic_probe': >> drivers//regulator/s5m8767.c:1001:31: error: 's5m8767_devm_gpiod_release' undeclared (first use in this function); did you mean 's5m8767_set_voltage_sel'? devres_destroy(&pdev->dev, s5m8767_devm_gpiod_release, ^~~~~~~~~~~~~~~~~~~~~~~~~~ s5m8767_set_voltage_sel drivers//regulator/s5m8767.c:1001:31: note: each undeclared identifier is reported only once for each function it appears in >> drivers//regulator/s5m8767.c:1002:12: error: 's5m8767_devm_gpiod_match' undeclared (first use in this function); did you mean 's5m8767_devm_gpiod_release'? s5m8767_devm_gpiod_match, ^~~~~~~~~~~~~~~~~~~~~~~~ s5m8767_devm_gpiod_release vim +1001 drivers//regulator/s5m8767.c 718 719 static int s5m8767_pmic_probe(struct platform_device *pdev) 720 { 721 struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); 722 struct sec_platform_data *pdata = iodev->pdata; 723 struct regulator_config config = { }; 724 struct s5m8767_info *s5m8767; 725 int i, ret, buck_init; 726 727 if (!pdata) { 728 dev_err(pdev->dev.parent, "Platform data not supplied\n"); 729 return -ENODEV; 730 } 731 732 if (iodev->dev->of_node) { 733 ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata); 734 if (ret) 735 return ret; 736 } 737 738 if (pdata->buck2_gpiodvs) { 739 if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) { 740 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); 741 return -EINVAL; 742 } 743 } 744 745 if (pdata->buck3_gpiodvs) { 746 if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) { 747 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); 748 return -EINVAL; 749 } 750 } 751 752 if (pdata->buck4_gpiodvs) { 753 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) { 754 dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n"); 755 return -EINVAL; 756 } 757 } 758 759 s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info), 760 GFP_KERNEL); 761 if (!s5m8767) 762 return -ENOMEM; 763 764 s5m8767->dev = &pdev->dev; 765 s5m8767->iodev = iodev; 766 s5m8767->num_regulators = pdata->num_regulators; 767 platform_set_drvdata(pdev, s5m8767); 768 769 s5m8767->buck_gpioindex = pdata->buck_default_idx; 770 s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs; 771 s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs; 772 s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs; 773 s5m8767->buck_gpios[0] = pdata->buck_gpios[0]; 774 s5m8767->buck_gpios[1] = pdata->buck_gpios[1]; 775 s5m8767->buck_gpios[2] = pdata->buck_gpios[2]; 776 s5m8767->buck_ds[0] = pdata->buck_ds[0]; 777 s5m8767->buck_ds[1] = pdata->buck_ds[1]; 778 s5m8767->buck_ds[2] = pdata->buck_ds[2]; 779 780 s5m8767->ramp_delay = pdata->buck_ramp_delay; 781 s5m8767->buck2_ramp = pdata->buck2_ramp_enable; 782 s5m8767->buck3_ramp = pdata->buck3_ramp_enable; 783 s5m8767->buck4_ramp = pdata->buck4_ramp_enable; 784 s5m8767->opmode = pdata->opmode; 785 786 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, 787 pdata->buck2_init); 788 789 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2, 790 buck_init); 791 792 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, 793 pdata->buck3_init); 794 795 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2, 796 buck_init); 797 798 buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2, 799 pdata->buck4_init); 800 801 regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2, 802 buck_init); 803 804 for (i = 0; i < 8; i++) { 805 if (s5m8767->buck2_gpiodvs) { 806 s5m8767->buck2_vol[i] = 807 s5m8767_convert_voltage_to_sel( 808 &buck_voltage_val2, 809 pdata->buck2_voltage[i]); 810 } 811 812 if (s5m8767->buck3_gpiodvs) { 813 s5m8767->buck3_vol[i] = 814 s5m8767_convert_voltage_to_sel( 815 &buck_voltage_val2, 816 pdata->buck3_voltage[i]); 817 } 818 819 if (s5m8767->buck4_gpiodvs) { 820 s5m8767->buck4_vol[i] = 821 s5m8767_convert_voltage_to_sel( 822 &buck_voltage_val2, 823 pdata->buck4_voltage[i]); 824 } 825 } 826 827 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || 828 pdata->buck4_gpiodvs) { 829 830 if (!gpio_is_valid(pdata->buck_gpios[0]) || 831 !gpio_is_valid(pdata->buck_gpios[1]) || 832 !gpio_is_valid(pdata->buck_gpios[2])) { 833 dev_err(&pdev->dev, "GPIO NOT VALID\n"); 834 return -EINVAL; 835 } 836 837 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0], 838 "S5M8767 SET1"); 839 if (ret) 840 return ret; 841 842 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1], 843 "S5M8767 SET2"); 844 if (ret) 845 return ret; 846 847 ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2], 848 "S5M8767 SET3"); 849 if (ret) 850 return ret; 851 852 /* SET1 GPIO */ 853 gpio_direction_output(pdata->buck_gpios[0], 854 (s5m8767->buck_gpioindex >> 2) & 0x1); 855 /* SET2 GPIO */ 856 gpio_direction_output(pdata->buck_gpios[1], 857 (s5m8767->buck_gpioindex >> 1) & 0x1); 858 /* SET3 GPIO */ 859 gpio_direction_output(pdata->buck_gpios[2], 860 (s5m8767->buck_gpioindex >> 0) & 0x1); 861 } 862 863 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2"); 864 if (ret) 865 return ret; 866 867 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3"); 868 if (ret) 869 return ret; 870 871 ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4"); 872 if (ret) 873 return ret; 874 875 /* DS2 GPIO */ 876 gpio_direction_output(pdata->buck_ds[0], 0x0); 877 /* DS3 GPIO */ 878 gpio_direction_output(pdata->buck_ds[1], 0x0); 879 /* DS4 GPIO */ 880 gpio_direction_output(pdata->buck_ds[2], 0x0); 881 882 if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs || 883 pdata->buck4_gpiodvs) { 884 regmap_update_bits(s5m8767->iodev->regmap_pmic, 885 S5M8767_REG_BUCK2CTRL, 1 << 1, 886 (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1)); 887 regmap_update_bits(s5m8767->iodev->regmap_pmic, 888 S5M8767_REG_BUCK3CTRL, 1 << 1, 889 (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1)); 890 regmap_update_bits(s5m8767->iodev->regmap_pmic, 891 S5M8767_REG_BUCK4CTRL, 1 << 1, 892 (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1)); 893 } 894 895 /* Initialize GPIO DVS registers */ 896 for (i = 0; i < 8; i++) { 897 if (s5m8767->buck2_gpiodvs) { 898 regmap_write(s5m8767->iodev->regmap_pmic, 899 S5M8767_REG_BUCK2DVS1 + i, 900 s5m8767->buck2_vol[i]); 901 } 902 903 if (s5m8767->buck3_gpiodvs) { 904 regmap_write(s5m8767->iodev->regmap_pmic, 905 S5M8767_REG_BUCK3DVS1 + i, 906 s5m8767->buck3_vol[i]); 907 } 908 909 if (s5m8767->buck4_gpiodvs) { 910 regmap_write(s5m8767->iodev->regmap_pmic, 911 S5M8767_REG_BUCK4DVS1 + i, 912 s5m8767->buck4_vol[i]); 913 } 914 } 915 916 if (s5m8767->buck2_ramp) 917 regmap_update_bits(s5m8767->iodev->regmap_pmic, 918 S5M8767_REG_DVSRAMP, 0x08, 0x08); 919 920 if (s5m8767->buck3_ramp) 921 regmap_update_bits(s5m8767->iodev->regmap_pmic, 922 S5M8767_REG_DVSRAMP, 0x04, 0x04); 923 924 if (s5m8767->buck4_ramp) 925 regmap_update_bits(s5m8767->iodev->regmap_pmic, 926 S5M8767_REG_DVSRAMP, 0x02, 0x02); 927 928 if (s5m8767->buck2_ramp || s5m8767->buck3_ramp 929 || s5m8767->buck4_ramp) { 930 unsigned int val; 931 switch (s5m8767->ramp_delay) { 932 case 5: 933 val = S5M8767_DVS_BUCK_RAMP_5; 934 break; 935 case 10: 936 val = S5M8767_DVS_BUCK_RAMP_10; 937 break; 938 case 25: 939 val = S5M8767_DVS_BUCK_RAMP_25; 940 break; 941 case 50: 942 val = S5M8767_DVS_BUCK_RAMP_50; 943 break; 944 case 100: 945 val = S5M8767_DVS_BUCK_RAMP_100; 946 break; 947 default: 948 val = S5M8767_DVS_BUCK_RAMP_10; 949 } 950 regmap_update_bits(s5m8767->iodev->regmap_pmic, 951 S5M8767_REG_DVSRAMP, 952 S5M8767_DVS_BUCK_RAMP_MASK, 953 val << S5M8767_DVS_BUCK_RAMP_SHIFT); 954 } 955 956 for (i = 0; i < pdata->num_regulators; i++) { 957 const struct sec_voltage_desc *desc; 958 int id = pdata->regulators[i].id; 959 int enable_reg, enable_val; 960 struct regulator_dev *rdev; 961 962 desc = reg_voltage_map[id]; 963 if (desc) { 964 regulators[id].n_voltages = 965 (desc->max - desc->min) / desc->step + 1; 966 regulators[id].min_uV = desc->min; 967 regulators[id].uV_step = desc->step; 968 regulators[id].vsel_reg = 969 s5m8767_get_vsel_reg(id, s5m8767); 970 if (id < S5M8767_BUCK1) 971 regulators[id].vsel_mask = 0x3f; 972 else 973 regulators[id].vsel_mask = 0xff; 974 975 ret = s5m8767_get_register(s5m8767, id, &enable_reg, 976 &enable_val); 977 if (ret) { 978 dev_err(s5m8767->dev, "error reading registers\n"); 979 return ret; 980 } 981 regulators[id].enable_reg = enable_reg; 982 regulators[id].enable_mask = S5M8767_ENCTRL_MASK; 983 regulators[id].enable_val = enable_val; 984 } 985 986 config.dev = s5m8767->dev; 987 config.init_data = pdata->regulators[i].initdata; 988 config.driver_data = s5m8767; 989 config.regmap = iodev->regmap_pmic; 990 config.of_node = pdata->regulators[i].reg_node; 991 config.ena_gpiod = NULL; 992 if (pdata->regulators[i].ext_control_gpiod) { 993 /* Assigns config.ena_gpiod */ 994 s5m8767_regulator_config_ext_control(s5m8767, 995 &pdata->regulators[i], &config); 996 997 /* 998 * Hand the GPIO descriptor management over to the 999 * regulator core, remove it from devres management. 1000 */ > 1001 devres_destroy(&pdev->dev, s5m8767_devm_gpiod_release, > 1002 s5m8767_devm_gpiod_match, 1003 config.ena_gpiod); 1004 } 1005 rdev = devm_regulator_register(&pdev->dev, ®ulators[id], 1006 &config); 1007 if (IS_ERR(rdev)) { 1008 ret = PTR_ERR(rdev); 1009 dev_err(s5m8767->dev, "regulator init failed for %d\n", 1010 id); 1011 return ret; 1012 } 1013 1014 if (pdata->regulators[i].ext_control_gpiod) { 1015 ret = s5m8767_enable_ext_control(s5m8767, rdev); 1016 if (ret < 0) { 1017 dev_err(s5m8767->dev, 1018 "failed to enable gpio control over %s: %d\n", 1019 rdev->desc->name, ret); 1020 return ret; 1021 } 1022 } 1023 } 1024 1025 return 0; 1026 } 1027 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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.config.gz
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