[PATCH v3 5/6] DEV: CLK: sunxi ccu: export clk_apb1 for sun8i-r40 soc pwm.

[Hao Zhang <hao5781286@xxxxxxxxx>]

The clock source for sun8i R40 is from apb1, so export it for
dt parses.

Signed-off-by: Hao Zhang <hao5781286@xxxxxxxxx>
---
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h      | 4 +++-
 include/dt-bindings/clock/sun8i-r40-ccu.h | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
index db2a124..181ab26 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
@@ -51,7 +51,9 @@
 
 #define CLK_AXI			25
 #define CLK_AHB1		26
-#define CLK_APB1		27
+
+/* The APB1 clock is exported */
+
 #define CLK_APB2		28
 
 /* All the bus gates are exported */
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
index f9e15a2..a2b8f06 100644
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -49,6 +49,8 @@
 
 #define CLK_CPU			24
 
+#define CLK_APB1                27
+
 #define CLK_BUS_MIPI_DSI	29
 #define CLK_BUS_CE		30
 #define CLK_BUS_DMA		31
-- 
2.7.4