Re: [PATCH v2 3/5] clk: lochnagar: Add support for the Cirrus Logic Lochnagar

[Stephen Boyd <sboyd@xxxxxxxxxx>]

Quoting Charles Keepax (2018-10-11 06:26:02)
> On Thu, Oct 11, 2018 at 12:00:46AM -0700, Stephen Boyd wrote:
> > Quoting Charles Keepax (2018-10-08 06:25:40)
> 
> > > +struct lochnagar_regmap_clk {
> > > +       unsigned int cfg_reg;
> > > +       unsigned int ena_mask;
> > > +       unsigned int dir_mask;
> > > +
> > > +       unsigned int src_reg;
> > > +       unsigned int src_mask;
> > 
> > Are these 32 bits or 16 bits or 8 bits? Please use a u32/u16/u8 so we
> > know the register width.
> > 
> 
> Can do.

Well Mark may be opposed so it doesn't really matter to me. Just
would be nice to have some more code documentation on the expected
register width.

> 
> > > +struct lochnagar_clk_priv {
> > > +       struct device *dev;
> > > +       struct lochnagar *lochnagar;
> > 
> > Is this used for anything besides getting the regmap? Can you get the
> > pointer to the parent in probe and use that to get the regmap pointer
> > from dev_get_remap() and also use the of_node of the parent to register
> > a clk provider? It would be nice to avoid including the mfd header file
> > unless it's providing something useful.
> > 
> 
> It is also used to find out which type of Lochnagar we have
> connected, which determines which clocks we should register. I

Can that be done through some device ID? So the driver can be untangled
from the MFD part.

> could perhaps pass that using another mechanism but we would
> still want to include the MFD stuff to get the register
> definitions. So this approach seems simplest.

Can the register definitions be moved to this clk driver?

Maybe you now get the hint, but I'd really like to be able to merge and
compile the clk driver all by itself without relying on the parent MFD
device to provide anything at compile time.

> 
> > > +#define LN_CLK_FIXED(ID, NAME, RATE) \
> > > +       [LOCHNAGAR_##ID] = { \
> > > +               .name = NAME, .type = LOCHNAGAR_CLK_TYPE_FIXED, \
> > > +               { .fixed.rate = RATE, }, \
> > > +       }
> > 
> > Can all these fixed clks come from DT instead of being populated by this
> > driver? Unless they're being generated by this hardware block and not
> > actually a crystal or some other on-board clock that goes into this
> > hardware block and then right out of it?
> > 
> 
> Technically they are supplied by a clock generator chip (bunch of
> PLLs) which is controlled by the board controller chip. That said
> I don't really ever see them changing so will move them in DT.
> 
> > > +static int lochnagar_regmap_prepare(struct clk_hw *hw)
> > > +{
> > > +       struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
> > > +       struct lochnagar_clk_priv *priv = lclk->priv;
> > > +       struct regmap *regmap = priv->lochnagar->regmap;
> > > +       int ret;
> > > +
> > > +       dev_dbg(priv->dev, "Prepare %s\n", lclk->name);
> > 
> > Nitpick: Can you just rely on the clk tracepoints?
> > 
> 
> Can do they are hardly essential.
> 
> > > +
> > > +       if (!lclk->regmap.ena_mask)
> > 
> > Why did we assign the ops to the clk if it can't be enabled? Please make
> > different ops for different types of clks so we don't have to check
> > something else and bail out early when the op is called.
> > 
> 
> This is a bit of a leak from earlier versions of the code I
> can just remove them.
> 
> > > +static int lochnagar_regmap_set_parent(struct clk_hw *hw, u8 index)
> > > +{
> > > +       struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
> > > +       struct lochnagar_clk_priv *priv = lclk->priv;
> > > +       struct regmap *regmap = priv->lochnagar->regmap;
> > > +       int ret;
> > > +
> > > +       dev_dbg(priv->dev, "Reparent %s to %s\n",
> > > +               lclk->name, priv->parents[index]);
> > > +
> > > +       if (lclk->regmap.dir_mask) {
> > > +               ret = regmap_update_bits(regmap, lclk->regmap.cfg_reg,
> > > +                                        lclk->regmap.dir_mask,
> > > +                                        lclk->regmap.dir_mask);
> > > +               if (ret < 0) {
> > > +                       dev_err(priv->dev, "Failed to set %s direction: %d\n",
> > 
> > What does direction mean?
> > 
> 
> Some of the clocks can both generate and receive a clock. For
> example the PSIA (external audio interface) MCLKs, the attached
> device could be expecting or providing a master audio clock. If
> the user assigns a parent to the clock we assume the attached
> device is providing a clock to us, otherwise we assume we are
> providing the clock.

And this directionality is determined by dir_mask? It would be great if
this sort of information was in the commit text or in a comment in the
driver so we know what's going on here.

> 
> > > +static int lochnagar_clk_remove(struct platform_device *pdev)
> > > +{
> > > +       struct lochnagar_clk_priv *priv = platform_get_drvdata(pdev);
> > > +       int i;
> > > +
> > > +       of_clk_del_provider(priv->lochnagar->dev->of_node);
> > 
> > Use devm variant of clk provider registration?
> > 
> 
> This isn't using the devm version as it makes the assumption
> that the device that contains the DT is the same one we want
> to devm against which isn't the case here.
> 
> I could update probe to copy the of_node over from the parent, if
> you prefer? I think that would also work.

I don't really mind either way. When we get these subdevice drivers of a
larger OF node for the whole MFD it becomes sort of awkward to make devm
work.