Re: [PATCH 1/2] MIPS: mscc: ocelot: add interrupt controller properties to GPIO controller

[Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx>]

On 25/07/2018 14:26:20+0200, Quentin Schulz wrote:
> The GPIO controller also serves as an interrupt controller for events
> on the GPIO it handles.
> 
> An interrupt occurs whenever a GPIO line has changed.
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@xxxxxxxxxxx>
Acked-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxx>

> ---
>  arch/mips/boot/dts/mscc/ocelot.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
> index d7f0e3551500..afe8fc9011ea 100644
> --- a/arch/mips/boot/dts/mscc/ocelot.dtsi
> +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
> @@ -168,6 +168,9 @@
>  			gpio-controller;
>  			#gpio-cells = <2>;
>  			gpio-ranges = <&gpio 0 0 22>;
> +			interrupt-controller;
> +			interrupts = <13>;
> +			#interrupt-cells = <2>;
>  
>  			uart_pins: uart-pins {
>  				pins = "GPIO_6", "GPIO_7";
> -- 
> 2.14.1
> 

-- 
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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