On 18 June 2018 at 14:23, Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> wrote: > The Aspeed GPIO hardware has a quirk: the value register, for an > output GPIO, doesn't contain the last value written (the write > latch content) but the sampled input value. > > This means that when reading back shortly after writing, you can > get an incorrect value as the input value is delayed by a few > synchronizers. > > The HW supports a separate read-only register "Data Read Register" > which allows you to read the write latch instead. > > This adds the definition for it, and uses it for the initial > population of the GPIO value cache. It will be used more in > subsequent patches. > can be > > Signed-off-by: Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx> Reviewed-by: Joel Stanley <joel@xxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html