On Thu, 2018-03-29 at 17:37 +0300, Mika Westerberg wrote: > It turns out that the Windows GPIO driver for Sunrisepoint PCH-H uses > similar bank structure than it does for Cannon Lake with the exception > that here the bank size is always 24 pins. Starting from pad group E > the > BIOS/Windows GPIO numbering does not match the hardware anymore but > instead there are gaps to make each pad group ("bank") consume exactly > 24 pins. Because of this Linux does not use correct pins for > GpioIo/GpioIo resources exposed by the BIOS. > > This patch aligns the GPIO number space with BIOS/Windows to make sure > the same numbering scheme is used in Linux as well following what we > did > already for Intel Cannon Lake. > > Link: https://bugzilla.redhat.com/show_bug.cgi?id=1543769 > Reported-by: Vivien FRASCA <vivien.frasca@xxxxxxxxx> Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Given what Hans said I agree we need this to go stable (I'm not fan of reverting that will break other chips). > Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > --- > This should go to stable as well with following tags > > Fixes: 551fa5801ef1 ("pinctrl: intel: sunrisepoint: Add Intel > Sunrisepoint-H support") > Cc: stable@xxxxxxxxxxxxxxx > > but there is dependency to following commits as well: > > 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO > translation") > a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad > groups") > > I'm not sure whether they can be considered as stable material, > though. > > drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 45 > ++++++++++++++++++++++++++-- > 1 file changed, 42 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c > b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c > index 8870a4100164..fee3435a6f15 100644 > --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c > +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c > @@ -36,6 +36,27 @@ > .npins = ((e) - (s) + 1), \ > } > > +#define SPTH_GPP(r, s, e, g) \ > + { \ > + .reg_num = (r), \ > + .base = (s), \ > + .size = ((e) - (s) + 1), \ > + .gpio_base = (g), \ > + } > + > +#define SPTH_COMMUNITY(b, s, e, g) \ > + { \ > + .barno = (b), \ > + .padown_offset = SPT_PAD_OWN, \ > + .padcfglock_offset = SPT_PADCFGLOCK, \ > + .hostown_offset = SPT_HOSTSW_OWN, \ > + .ie_offset = SPT_GPI_IE, \ > + .pin_base = (s), \ > + .npins = ((e) - (s) + 1), \ > + .gpps = (g), \ > + .ngpps = ARRAY_SIZE(g), \ > + } > + > /* Sunrisepoint-LP */ > static const struct pinctrl_pin_desc sptlp_pins[] = { > /* GPP_A */ > @@ -531,10 +552,28 @@ static const struct intel_function > spth_functions[] = { > FUNCTION("i2c2", spth_i2c2_groups), > }; > > +static const struct intel_padgroup spth_community0_gpps[] = { > + SPTH_GPP(0, 0, 23, 0), /* GPP_A */ > + SPTH_GPP(1, 24, 47, 24), /* GPP_B */ > +}; > + > +static const struct intel_padgroup spth_community1_gpps[] = { > + SPTH_GPP(0, 48, 71, 48), /* GPP_C */ > + SPTH_GPP(1, 72, 95, 72), /* GPP_D */ > + SPTH_GPP(2, 96, 108, 96), /* GPP_E */ > + SPTH_GPP(3, 109, 132, 120), /* GPP_F */ > + SPTH_GPP(4, 133, 156, 144), /* GPP_G */ > + SPTH_GPP(5, 157, 180, 168), /* GPP_H */ > +}; > + > +static const struct intel_padgroup spth_community3_gpps[] = { > + SPTH_GPP(0, 181, 191, 192), /* GPP_I */ > +}; > + > static const struct intel_community spth_communities[] = { > - SPT_COMMUNITY(0, 0, 47), > - SPT_COMMUNITY(1, 48, 180), > - SPT_COMMUNITY(2, 181, 191), > + SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps), > + SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps), > + SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps), > }; > > static const struct intel_pinctrl_soc_data spth_soc_data = { -- Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Intel Finland Oy -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html