Re: [PATCH v2 00/16] gpio: Tight IRQ chip integration and banked infrastructure

[Linus Walleij <linus.walleij@xxxxxxxxxx>]

On Mon, Oct 2, 2017 at 9:55 AM, Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:

> This is not necessarily a blocker if it can be shown that others than
> TI/OMAP can reuse it.
>
> I've looked at things like the imagination pistachio:
>
> pinctrl@18101C00 {
>         compatible = "img,pistachio-system-pinctrl";
>         reg = <0x18101C00 0x400>;
>
>         gpio0: gpio0 {
>                 interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
>
>                 gpio-controller;
>                 #gpio-cells = <2>;
>
>                 interrupt-controller;
>                 #interrupt-cells = <2>;
>         };
>
>         ...
>
>         gpio5: gpio5 {
>                 interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
>
>                 gpio-controller;
>                 #gpio-cells = <2>;
>
>                 interrupt-controller;
>                 #interrupt-cells = <2>;
>         };
>
> This looks like a clear candidate.
> CC: to  Andrew Bresticker, can you look into this?
>
> Another example would be gpio-tz1090, notably with interrupt optional:
>
>        gpios: gpio-controller@02005800 {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>                 compatible = "img,tz1090-gpio";
>                 reg = <0x02005800 0x90>;
>
>                 /* bank 0 with an interrupt */
>                 gpios0: bank@0 {
>                         #gpio-cells = <2>;
>                         #interrupt-cells = <2>;
>                         reg = <0>;
>                         interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
>                         gpio-controller;
>                         gpio-ranges = <&pinctrl 0 0 30>;
>                         interrupt-controller;
>                 };
>
>                 /* bank 2 without interrupt */
>                 gpios2: bank@2 {
>                         #gpio-cells = <2>;
>                         reg = <2>;
>                         gpio-controller;
>                         gpio-ranges = <&pinctrl 0 60 30>;
>                 };
>         };
>
> CC to James Hogan to look at the series from this perspective.
>
> A third is gpio-mxs.c:
>
> pinctrl@80018000 {
>         compatible = "fsl,imx28-pinctrl", "simple-bus";
>         reg = <0x80018000 2000>;
>
>         gpio0: gpio@0 {
>                 compatible = "fsl,imx28-gpio";
>                 interrupts = <127>;
>                 gpio-controller;
>                 #gpio-cells = <2>;
>                 interrupt-controller;
>                 #interrupt-cells = <2>;
>         };
>
>         gpio1: gpio@1 {
>                 compatible = "fsl,imx28-gpio";
>                 interrupts = <126>;
>                 gpio-controller;
>                 #gpio-cells = <2>;
>                 interrupt-controller;
>                 #interrupt-cells = <2>;
>         };
>
>         gpio2: gpio@2 {
>                 compatible = "fsl,imx28-gpio";
>                 interrupts = <125>;
>                 gpio-controller;
>                 #gpio-cells = <2>;
>                 interrupt-controller;
>                 #interrupt-cells = <2>;
>         };
> (...)
>
> CC to Shawn Guo to look into this.
>
> So in short I think there can be others that can make good use of this
> infrastructure.

It also looks like the "ports" in the gpio-dwapb can be modeled using this
bank infrastructure, cutting down on per-driver overhead and adding
good much needed abstraction for these ports/banks.

Paging Hoan Tran on this as well, to keep an eye on the series.

Yours,
Linus Walleij
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