Re: [PATCH] pinctrl: mxs: atomically switch mux and drive strength config

[Linus Walleij <linus.walleij@xxxxxxxxxx>]

On Thu, May 18, 2017 at 11:23 AM, Uwe Kleine-König
<u.kleine-koenig@xxxxxxxxxxxxxx> wrote:

> To set the mux mode of a pin two bits must be set. Up to now this is
> implemented using the following idiom:
>
>         writel(mask, reg + CLR);
>         writel(value, reg + SET);
>
> . This however results in the mux mode being 0 between the two writes.
>
> On my machine there is an IC's reset pin connected to LCD_D20. The
> bootloader configures this pin as GPIO output-high (i.e. not holding the
> IC in reset). When Linux reconfigures the pin to GPIO the short time
> LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
> the connected IC.
>
> The same problem is present for the pin's drive strength setting which is
> reset to low drive strength before using the right value.
>
> So instead of relying on the hardware to modify the register setting
> using two writes implement the bit toggling using read-modify-write.
>
> Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx>

Patch applied for fixes with Shawn's ACK.

Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html