The offset for the PLL lock status register was incorrectly set to 0x208, which actually points to an unused register. The correct register offset is 0x20c. Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> --- drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c index 4a201a7e03b8..a9c5cc87d9d0 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c @@ -28,7 +28,7 @@ #include "ccu-sun8i-a83t.h" -#define CCU_SUN8I_A83T_LOCK_REG 0x208 +#define CCU_SUN8I_A83T_LOCK_REG 0x20c /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] clk: sunxi-ng: a83t: Fix PLL lock status register offset
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- Subject: [PATCH 1/6] clk: sunxi-ng: a83t: Fix PLL lock status register offset
- From: Chen-Yu Tsai <wens@xxxxxxxx>
- Date: Mon, 22 May 2017 14:25:47 +0800
- In-reply-to: <20170522062552.19026-1-wens@csie.org>
- References: <20170522062552.19026-1-wens@csie.org>
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- [PATCH 0/6] ARM: sun8i: a83t: Enable SPDIF output support
- From: Chen-Yu Tsai
- [PATCH 0/6] ARM: sun8i: a83t: Enable SPDIF output support
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