RE: [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and shift property

["A.S. Dong" <aisheng.dong@xxxxxxx>]

> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@xxxxxxxxxx]
> Sent: Monday, May 15, 2017 6:59 PM
> To: A.S. Dong
> Cc: Andy Duan; Jacky Bai; linus.walleij@xxxxxxxxxx; stefan@xxxxxxxx;
> linux-gpio@xxxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx; linux-arm-
> kernel@xxxxxxxxxxxxxxxxxxx
> Subject: Re: [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and
> shift property
> 
> On Mon, May 15, 2017 at 09:00:32AM +0000, A.S. Dong wrote:
> > > > @@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev
> > > *pctldev,
> > > >  	*config = readl(ipctl->base + pin_reg->conf_reg);
> > > >
> > > >  	if (info->flags & SHARE_MUX_CONF_REG)
> > > > -		*config &= 0xffff;
> > > > +		*config &= ~info->mux_mask;
> > >
> > > It changes the way how code works.  We need a note in the commit log
> > > explaining why it's safe.
> > >
> >
> > Well, that's Vybrid tricks that BIT[15-0] are all configs part.
> > So it hardcoded 0xffff there.
> >
> > But it's not true in ULP, so use mux_mask instead to address the
> > difference.
> 
> So you make the assumption that for all SHARE_MUX_CONF_REG SoCs, all bits
> in the register except mux ones are config bits.  You at least need to
> mention that in the commit log, IMO.

Yes, it's true, at least for all current known SoCs.
But your suggestion is good, I can add it in commit log.

Thanks

Regards
Dong Aisheng

> 
> Shawn
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