Hi Boris, Linus,
On 30/03/17 12:29, Boris Brezillon wrote:
Hi Linus,
On Thu, 30 Mar 2017 11:03:45 +0200
Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
On Wed, Mar 29, 2017 at 6:04 PM, Boris Brezillon
<boris.brezillon@xxxxxxxxxxxxxxxxxx> wrote:
Add a driver for Cadence GPIO controller.
IIUC Cadence do a lot of things. Are there variants of this controller?
I'll let Simon answer that one.
This is a controller that has been around since 2000. It is not
configurable in any way, so there are no variants. Cadence do not offer
any other GPIO controllers as IP.
+static irqreturn_t cdns_gpio_irq_handler(int irq, void *dev)
+{
+ struct cdns_gpio_chip *cgpio = dev;
+ unsigned long status;
+ int hwirq;
+
+ /*
+ * FIXME: If we have an edge irq that is masked we might lose it
+ * since reading the STATUS register clears all IRQ flags.
+ * We could store the status of all masked IRQ in the cdns_gpio_chip
+ * struct but we then have no way to re-trigger the interrupt when
+ * it is unmasked.
+ */
It is marked FIXME but do you think it can even be fixed? It seems
like a hardware flaw. :(
Maybe not. Unless Simon comes up with a magic register to re-trigger an
interrupt :-).
There are no plans to update the controller.
Another solution would be to write 0xffffffff into CDNS_GPIO_OUTPUT_EN
at probe time so that each time CDNS_GPIO_DIRECTION_MODE is modified to
set a pin in output mode, the CDNS_GPIO_OUTPUT_EN is already correctly
configured.
Simon, would that work? Is there a good reason to keep a bit in
CDNS_GPIO_OUTPUT_EN set to 0 when the GPIO is in input mode (power
consumption?)?
If direction_mode is set to input then output_en is ignored so this
should work. The hardware defaults to output mode, so as long as you
set all pins to input mode before you set all output_en bits there
should be no negative effect.
Cheers,
-- Simon
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