On Mon, Jan 9, 2017 at 4:00 PM, Imran Khan <kimran@xxxxxxxxxxxxxx> wrote: > Add initial pinctrl driver to support pin configuration with > pinctrl framework for msm8998. > > Signed-off-by: Imran Khan <kimran@xxxxxxxxxxxxxx> You need review from the Qcom pinctrl maintainer Bjorn Andersson for this patch. +#define NORTH 0x500000 +#define WEST 0x100000 +#define EAST 0x900000 (...) > +static const struct msm_pingroup msm8998_groups[] = { > + PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA, (...) > + PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, NA, NA, NA, NA, (...) > + PINGROUP(35, NORTH, pci_e0, jitter_bist, NA, NA, NA, NA, NA, NA, NA), (...) No south? :) Are these the left/right/top edges of the chip or a reference to x86 bridges terminology? It warrants that you add a comment to the driver file explaining what it means. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html