On Tue, Nov 08, 2016 at 04:57:18PM +0800, Tan Jui Nee wrote: > From: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> > > There is already one and at least one more user coming which > require an access to Primary to Sideband bridge (P2SB) in order > to get IO or MMIO bar hidden by BIOS. > Create a driver to access P2SB for x86 devices. > > Signed-off-by: Yong, Jonathan <jonathan.yong@xxxxxxxxx> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Reviewed-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
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- Subject: Re: [PATCH v9 1/6] x86/platform/p2sb: New Primary to Sideband bridge support driver for Intel SOC's
- From: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
- Date: Tue, 8 Nov 2016 13:01:48 +0200
- In-reply-to: <1478595443-6306-2-git-send-email-jui.nee.tan@intel.com>
- Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
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