On Wed, Sep 28, 2016 at 12:20 AM, Andrew Jeffery <andrew@xxxxxxxx> wrote: > The patch introducing the g4 pinctrl driver implemented a smattering of > pins to flesh out the implementation of the core and provide bare-bones > support for some OpenPOWER platforms. Now, update the bindings document > to reflect the complete functionality and implement the necessary pin > configuration tables in the driver. > > Cc: Timothy Pearson <tpearson@xxxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx> Acked-by: Joel Stanley <joel@xxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins
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- Subject: Re: [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins
- From: Joel Stanley <joel@xxxxxxxxx>
- Date: Thu, 29 Sep 2016 10:24:26 +0930
- In-reply-to: <e0d8fa6cd444972e6f048f98da98f0439e6ca39b.1474986045.git-series.andrew@aj.id.au>
- References: <cover.115463f791b69859c5ce9dafd61a5755ea039f4b.1474986045.git-series.andrew@aj.id.au> <e0d8fa6cd444972e6f048f98da98f0439e6ca39b.1474986045.git-series.andrew@aj.id.au>
- References:
- [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins
- From: Andrew Jeffery
- [PATCH 7/8] pinctrl: aspeed-g4: Add mux configuration for all pins
- From: Andrew Jeffery
- [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins
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