Re: Question about ASPEED GPIO value/direction set order

[Andrew Jeffery <andrew@xxxxxxxxxxxxxxxxxxxx>]

Hi Nikita,

On Thu, 2025-03-13 at 10:39 +0300, Nikita Shubin wrote:
> Hi Andrew, thank you for quick answer.
> 
> The reason i am asking this is that in QEMU the first time we set
> pin,
> all below if (diff) in aspeed_gpio_update() won't be triggered due to
> direction is set after the value itself (so no qemu_set_irq()
> triggers):
> 
> https://elixir.bootlin.com/qemu/v9.2.2/source/hw/gpio/aspeed_gpio.c#L314
> 
> aspeed # gpioset 0 8=1
> aspeed_gpio_write offset: 0x1c value 0x100
> aspeed_gpio_write offset: 0x0 value 0x100       <-- VALUE
> aspeed_gpio_write offset: 0x4 value 0x100       <-- DIRECTION
> 
> And i doubted if it's a QEMU or Linux driver flaw.

That sounds like a bug in the qemu model. Please send a patch to the
qemu lists for discussion.

Thanks,

Andrew