On 17.12.2024 10:13 AM, Manikanta Mylavarapu wrote: > Add SPI0 node for IPQ5424 SoC. > > Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@xxxxxxxxxxx> > --- > Changes in V2: > - No change > > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > index 5e219f900412..b4d736cd8610 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > @@ -201,6 +201,17 @@ uart1: serial@1a84000 { > clock-names = "se"; > interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; > }; > + > + spi0: spi@1a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x01a90000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_SPI0_CLK>; This register base suggests SPI4 for both the name and clock The existing UART1 similarly should be UART0 Konrad