Correct the gpio-ranges for the QCS615 TLMM pin controller to include GPIOs 0-122 and the UFS_RESET pin for primary UFS memory reset. Fixes: 8e266654a2fe ("arm64: dts: qcom: add QCS615 platform") Signed-off-by: Lijuan Gao <quic_lijuang@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index c0e4b376a1c6..4c3d8e39ce0b 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -938,7 +938,7 @@ tlmm: pinctrl@3100000 { "west", "south"; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-ranges = <&tlmm 0 0 123>; + gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; interrupt-controller; -- 2.46.0