Re: [PATCH v2 24/25] arm64: dts: renesas: rzg3s-smarc: Enable SSI3

[Claudiu Beznea <claudiu.beznea@xxxxxxxxx>]

Hi, Biju,

On 10.11.2024 10:54, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch.
> 
> 
>> -----Original Message-----
>> From: Claudiu <claudiu.beznea@xxxxxxxxx>
>> Sent: 08 November 2024 10:50
>> Subject: [PATCH v2 24/25] arm64: dts: renesas: rzg3s-smarc: Enable SSI3
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>>
>> Enable SSI3.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>> ---
>>
>> Changes in v2:
>> - none
>>
>>  arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 26 ++++++++++++++++++++
>>  1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-
>> smarc.dtsi
>> index 4aa99814b808..6dd439e68bd4 100644
>> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
>> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
>> @@ -64,6 +64,11 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
>>  	};
>>  };
>>
> 
> &audio_clk1 {
>        assigned-clocks = <&versa3 xx>;
>        clock-frequency = <11289600>;
> };

audio_clk1 node is in the RZ/G3S dtsi to keep the compilation happy.

For this board the audio clock1 for the SSI 3 is from <&versa3 2>.

If we fill in the audio_clk1 here it will be useless, there will be no
consumers for it and it is not available on board.

Thank you,
Claudiu Beznea

> 
> Maybe add audio_clk1, so that it described properly in clock tree??
> 
> Cheers,
> Biju
> 
>> +&audio_clk2 {
>> +	clock-frequency = <12288000>;
>> +	status = "okay";
>> +};
>> +
>>  &i2c0 {
>>  	status = "okay";
>>
>> @@ -94,6 +99,11 @@ da7212: codec@1a {
>>  };
>>
>>  &pinctrl {
>> +	audio_clock_pins: audio-clock {
>> +		pins = "AUDIO_CLK1", "AUDIO_CLK2";
>> +		input-enable;
>> +	};
>> +
>>  	key-1-gpio-hog {
>>  		gpio-hog;
>>  		gpios = <RZG2L_GPIO(18, 0) GPIO_ACTIVE_LOW>; @@ -151,6 +161,13 @@ cd {
>>  			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
>>  		};
>>  	};
>> +
>> +	ssi3_pins: ssi3 {
>> +		pinmux = <RZG2L_PORT_PINMUX(18, 2, 8)>, /* BCK */
>> +			 <RZG2L_PORT_PINMUX(18, 3, 8)>, /* RCK */
>> +			 <RZG2L_PORT_PINMUX(18, 4, 8)>, /* TXD */
>> +			 <RZG2L_PORT_PINMUX(18, 5, 8)>; /* RXD */
>> +	};
>>  };
>>
>>  &scif0 {
>> @@ -171,3 +188,12 @@ &sdhi1 {
>>  	max-frequency = <125000000>;
>>  	status = "okay";
>>  };
>> +
>> +&ssi3 {
>> +	clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
>> +		 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
>> +		 <&versa3 2>, <&audio_clk2>;
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&ssi3_pins>, <&audio_clock_pins>;
>> +	status = "okay";
>> +};
>> --
>> 2.39.2
>