Hi.
On 2024-10-30 08:32, Uwe Kleine-König wrote:
+ * Limitations:
+ * - No disable bit, so a disabled PWM is simulated by setting duty_cycle to 0
+ * - Only 8 concurrent waveform generators are available for 8 combinations of
+ * duty_cycle and period. Waveform generators are shared between 16 GPIO
+ * pins and 17 SIPO GPIO pins.
+ * - Supports only normal polarity.
+ * - On configuration the currently running period is completed.
Maybe I already asked before: Is there a public manual? If so, please
add a link here.
Currently there is no public manual for this. And the existing manual is
not that detailed.
+ /* Configure frequency divisor */
+ mask = WAVE_GEN_CYCLE_MASK(index % 4);
+ val = (period << __ffs(mask)) & mask;
FIELD_PREP please.
Per my understanding FIELD_PREP only work on compile time constants.
MvH
Benjamin Larsson
