Re: [PATCH v3 1/3] dt-bindings: pinctrl: Add support for Amlogic A4 SoCs

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On 18/10/2024 12:13, Krzysztof Kozlowski wrote:
On 18/10/2024 11:20, Jerome Brunet wrote:
On Fri 18 Oct 2024 at 17:01, Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx> wrote:

Hi Jerome,
    Thanks for your reply.

On 2024/10/18 16:39, Jerome Brunet wrote:
[ EXTERNAL EMAIL ]
On Fri 18 Oct 2024 at 10:28, Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote:

On 18/10/2024 10:10, Xianwei Zhao via B4 Relay wrote:
From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>

Add the new compatible name for Amlogic A4 pin controller, and add
a new dt-binding header file which document the detail pin names.
the change does not do what is described here. At least the description
needs updating.


Will do.

So if the pin definition is now in the driver, does it mean that pins have
to be referenced in DT directly using the made up numbers that are
created in pinctrl-amlogic-a4.c at the beginning of patch #2 ?


Yes.

If that's case, it does not look very easy a read.


It does happen. The pin definition does not fall under the category of
binding.

https://lore.kernel.org/all/106f4321-59e8-49b9-bad3-eeb57627c921@xxxxxxxxxxx/

So the expectation is that people will write something like:

  reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;

And others will go in the driver to see that is maps to GPIOX_10 ? the number
being completly made up, with no link to anything HW/Datasheet
whatsoever ?

This is how things should be done now ?

Why would you need to do this? Why it cannot be <&gpio 10
GPIO_ACTIVE_LOW>, assuming it is GPIO 10?

Bindings have absolutely nothing to do with it. You have GPIO 10, not
42, right?

There's no 1:1 mapping between the number and the pin on Amlogic platforms,
so either a supplementary gpio phandle cell is needed to encode the gpio pin
group or some bindings header is needed to map those to well known identifiers.

Neil


Best regards,
Krzysztof






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