From: Konrad Dybcio <konradybcio@xxxxxxxxxx> Add DTS files for the A8X SoC and the only device based on it, the iPad Air 2. Signed-off-by: Konrad Dybcio <konradybcio@xxxxxxxxxx> [Markuss: System memory bits] Co-developed-by: Markuss Broks <markuss.broks@xxxxxxxxx> Signed-off-by: Markuss Broks <markuss.broks@xxxxxxxxx> [Nick: SMP, m1n1 and gpio-keys support, pinctrl fixes] Co-developed-by: Nick Chan <towinchenmi@xxxxxxxxx> Signed-off-by: Nick Chan <towinchenmi@xxxxxxxxx> --- arch/arm64/boot/dts/apple/Makefile | 2 + arch/arm64/boot/dts/apple/t7001-air2.dtsi | 46 +++++++ arch/arm64/boot/dts/apple/t7001-j81.dts | 14 ++ arch/arm64/boot/dts/apple/t7001-j82.dts | 14 ++ arch/arm64/boot/dts/apple/t7001.dtsi | 154 ++++++++++++++++++++++ 5 files changed, 230 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t7001-air2.dtsi create mode 100644 arch/arm64/boot/dts/apple/t7001-j81.dts create mode 100644 arch/arm64/boot/dts/apple/t7001-j82.dts create mode 100644 arch/arm64/boot/dts/apple/t7001.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index d5dd1e2e4f4c..adda522ea490 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -16,6 +16,8 @@ dtb-$(CONFIG_ARCH_APPLE) += t7000-j97.dtb dtb-$(CONFIG_ARCH_APPLE) += t7000-n102.dtb dtb-$(CONFIG_ARCH_APPLE) += t7000-n56.dtb dtb-$(CONFIG_ARCH_APPLE) += t7000-n61.dtb +dtb-$(CONFIG_ARCH_APPLE) += t7001-j81.dtb +dtb-$(CONFIG_ARCH_APPLE) += t7001-j82.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j274.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j293.dtb dtb-$(CONFIG_ARCH_APPLE) += t8103-j313.dtb diff --git a/arch/arm64/boot/dts/apple/t7001-air2.dtsi b/arch/arm64/boot/dts/apple/t7001-air2.dtsi new file mode 100644 index 000000000000..8ecf2842e8e5 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7001-air2.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad Air 2 common device tree + * Copyright (c) 2022, Konrad Dybcio <konradybcio@xxxxxxxxxx> + */ + +#include "t7001.dtsi" +#include <dt-bindings/input/input.h> + +/ { + chassis-type = "tablet"; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home Button"; + gpios = <&pinctrl 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + wakeup-source; + }; + + button-power { + label = "Power Button"; + gpios = <&pinctrl 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + wakeup-source; + }; + + button-volup { + label = "Volume Up"; + gpios = <&pinctrl 92 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-voldown { + label = "Volume Down"; + gpios = <&pinctrl 93 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t7001-j81.dts b/arch/arm64/boot/dts/apple/t7001-j81.dts new file mode 100644 index 000000000000..ca90dc0c872c --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7001-j81.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad Air 2 (Wi-Fi), J81, iPad5,3 (A1566) + * Copyright (c) 2022, Konrad Dybcio <konradybcio@xxxxxxxxxx> + */ + +/dts-v1/; + +#include "t7001-air2.dtsi" + +/ { + compatible = "apple,j81", "apple,t7001", "apple,arm-platform"; + model = "Apple iPad Air 2 (Wi-Fi)"; +}; diff --git a/arch/arm64/boot/dts/apple/t7001-j82.dts b/arch/arm64/boot/dts/apple/t7001-j82.dts new file mode 100644 index 000000000000..d9fd16f48db7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7001-j82.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad Air 2 (Cellular), J82, iPad5,4 (A1567) + * Copyright (c) 2022, Konrad Dybcio <konradybcio@xxxxxxxxxx> + */ + +/dts-v1/; + +#include "t7001-air2.dtsi" + +/ { + compatible = "apple,j82", "apple,t7001", "apple,arm-platform"; + model = "Apple iPad Air 2 (Cellular)"; +}; diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/apple/t7001.dtsi new file mode 100644 index 000000000000..9a5f0a4bde52 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T7001 "A8X" SoC + * + * Copyright (c) 2022, Konrad Dybcio <konradybcio@xxxxxxxxxx> + * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "apple,typhoon"; + reg = <0x0 0x0>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "apple,typhoon"; + reg = <0x0 0x1>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu2: cpu@2 { + compatible = "apple,typhoon"; + reg = <0x0 0x2>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + enable-method = "spin-table"; + device_type = "cpu"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0 0>; /* To be filled in by loader */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The bootloader reserves a region for the (varying-address, depending + * on what FW your device runs AND model) framebuffer under this node. + */ + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + serial0: serial@20a0c0000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x0a0c0000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + wdt: watchdog@20e027000 { + compatible = "apple,t7000-wdt", "apple,wdt"; + reg = <0x2 0x0e027000 0x0 0x1000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; + }; + + aic: interrupt-controller@20e100000 { + compatible = "apple,t7000-aic", "apple,aic"; + reg = <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + pinctrl: pinctrl@20e300000 { + compatible = "apple,t7000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0e300000 0x0 0x100000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 184>; + apple,npins = <184>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; +}; -- 2.46.0