Populate the GPIO node in the device tree for K1 SoC. Also, map all 128 pins as GPIO to the pinctrl controller. Signed-off-by: Yixun Lan <dlan@xxxxxxxxxx> --- arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index a2d5f7d4a942a..648b459597a4d 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -416,6 +416,19 @@ uart9: serial@d4017800 { status = "disabled"; }; + gpio: gpio@d4019000 { + compatible = "spacemit,k1-gpio"; + reg = <0x0 0xd4019000 0x0 0x800>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <58>; + interrupt-names = "gpio_mux"; + interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 0 128>; + }; + pinctrl: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; reg = <0x0 0xd401e000 0x0 0x400>; -- 2.45.2