On Tue, Jul 9, 2024 at 12:55 PM Huang-Huang Bao <i@xxxxxx> wrote: > The base iomux offsets for each GPIO pin line are accumulatively > calculated based off iomux width flag in rockchip_pinctrl_get_soc_data. > If the iomux width flag is one of IOMUX_WIDTH_4BIT, IOMUX_WIDTH_3BIT or > IOMUX_WIDTH_2BIT, the base offset for next pin line would increase by 8 > bytes, otherwise it would increase by 4 bytes. > > Despite most of GPIO2-B iomux have 2-bit data width, which can be fit > into 4 bytes space with write mask, it actually take 8 bytes width for > whole GPIO2-B line. > > Commit e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 > GPIO2-B pins") wrongly set iomux width flag to 0, causing all base > iomux offset for line after GPIO2-B to be calculated wrong. Fix the > iomux width flag to IOMUX_WIDTH_2BIT so the offset after GPIO2-B is > correctly increased by 8, matching the actual width of GPIO2-B iomux. > > Fixes: e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins") > Cc: stable@xxxxxxxxxxxxxxx > Reported-by: Richard Kojedzinszky <richard@xxxxxxxxx> > Closes: https://lore.kernel.org/linux-rockchip/4f29b743202397d60edfb3c725537415@xxxxxxxxx/ > Tested-by: Richard Kojedzinszky <richard@xxxxxxxxx> > Signed-off-by: Huang-Huang Bao <i@xxxxxx> Patch applied for fixes! Yours, Linus Walleij