On 18/08/2024 18:02, Andrew Lunn wrote:
Hi, per my understanding there is no public datasheet/register reference
manual.
But here is the division of regions of the registers in the gpio block and
how it is currently divided between the drivers (according to my current
understanding).
1FBF0200, gpio/pinctrl
1FBF0204, gpio/pinctrl
1FBF0208, gpio/pinctrl
1FBF020C, gpio/pinctrl
1FBF0210, gpio/pinctrl
1FBF0214, gpio/pinctrl
A typical SoC has multiple instances of a GPIO controller. Each GPIO
controller typically has 4 or 5 registers: In, Out, Direction,
Interrupt Enable, Interrupt Status. If these 4 or 5 registers are
contiguous, you could have one DT node per controller, rather than one
node for all GPIO controllers.
If the hardware designer has really messed up and fully interleaved
GPIO and PWM, it might be better to have an MFD. The MFD node has a
single reg covering the entire range. The MFD would then map the whole
range, and provide accessors to the child devices. Hard code the
knowledge of what registers are where. Given how badly the hardware is
designed, it is unlikely it will get reused in the future, so there is
no point putting lots of stuff into DT. Hard code it.
Andrew
Hi, the pwm driver could be re-used on the EN7523 SoC. Future Airoha
SoCs will most likely have the same ip-block also.
MvH
Benjamin Larsson
