> On Tue, Aug 13, 2024 at 10:06:41AM +0200, Benjamin Larsson wrote:
> > On 2024-08-12 08:48, Krzysztof Kozlowski wrote:
> > > > + pio: pinctrl@1fa20214 {
> > > > + compatible = "airoha,en7581-pinctrl";
> > > > + reg = <0x0 0x1fa20214 0x0 0x30>,
> > > > + <0x0 0x1fa2027c 0x0 0x8>,
> > > > + <0x0 0x1fbf0234 0x0 0x4>,
> > > > + <0x0 0x1fbf0268 0x0 0x4>,
> > > > + <0x0 0x1fa2001c 0x0 0x50>,
> > > > + <0x0 0x1fa2018c 0x0 0x4>,
> > > > + <0x0 0x1fbf0204 0x0 0x4>,
> > > > + <0x0 0x1fbf0270 0x0 0x4>,
> > > > + <0x0 0x1fbf0200 0x0 0x4>,
> > > > + <0x0 0x1fbf0220 0x0 0x4>,
> > > > + <0x0 0x1fbf0260 0x0 0x4>,
> > > > + <0x0 0x1fbf0264 0x0 0x4>,
> > > > + <0x0 0x1fbf0214 0x0 0x4>,
> > > > + <0x0 0x1fbf0278 0x0 0x4>,
> > > > + <0x0 0x1fbf0208 0x0 0x4>,
> > > > + <0x0 0x1fbf027c 0x0 0x4>,
> > > > + <0x0 0x1fbf0210 0x0 0x4>,
> > > > + <0x0 0x1fbf028c 0x0 0x4>,
> > > > + <0x0 0x1fbf0290 0x0 0x4>,
> > > > + <0x0 0x1fbf0294 0x0 0x4>,
> > > > + <0x0 0x1fbf020c 0x0 0x4>,
> > > > + <0x0 0x1fbf0280 0x0 0x4>,
> > > > + <0x0 0x1fbf0284 0x0 0x4>,
> > > > + <0x0 0x1fbf0288 0x0 0x4>;
> > > Why are you mapping individual registers? At least half of these are
> > > continuous.
> >
> > Hi, this is by design because of the register placement in the gpio block
> > and the fact that the pwm functionality is intermixed in there also. As
> > example the following registers are all GPIOCTRL:
> >
> > <0x0 0x1fbf0200 0x0 0x4>,
> > <0x0 0x1fbf0220 0x0 0x4>,
> > <0x0 0x1fbf0260 0x0 0x4>,
> > <0x0 0x1fbf0264 0x0 0x4>,
> >
> > To simplify the driver code logic the complexity is moved to the dts because
> > of that.
>
> DT to OS is an ABI. Don't put the complexity there. The driver is easy
> to change.
>
> Lot's of h/w blocks are just bit soup. This is not special. If a few
> regions is helpful, then that would be fine.
ack, I guess we can try to move the complexity in the driver, at least for
gpio-irq controllers, merging regs whenever possible. I will work on it.
Regards,
Lorenzo
>
> Rob
Attachment:
signature.asc
Description: PGP signature
