This is v2 of the same patch, sorry for missing to mention it in the commit. On Sat, Jul 27, 2024 at 6:30 PM Animesh Agarwal <animeshagarwal28@xxxxxxxxx> wrote: > > Convert the NXP LPC3220 SoC GPIO controller bindings to DT schema format. > > Cc: Daniel Baluta <daniel.baluta@xxxxxxx> > Signed-off-by: Animesh Agarwal <animeshagarwal28@xxxxxxxxx> > > -- > Changes in v2: > - Changed the file name to match the compatible string. > - Removed optional from the description of '#gpio-cells' as it was wrongly > present. > --- > .../devicetree/bindings/gpio/gpio_lpc32xx.txt | 43 --------------- > .../bindings/gpio/nxp,lpc3220-gpio.yaml | 52 +++++++++++++++++++ > 2 files changed, 52 insertions(+), 43 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt > create mode 100644 Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml > > diff --git a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt b/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt > deleted file mode 100644 > index 49819367a011..000000000000 > --- a/Documentation/devicetree/bindings/gpio/gpio_lpc32xx.txt > +++ /dev/null > @@ -1,43 +0,0 @@ > -NXP LPC32xx SoC GPIO controller > - > -Required properties: > -- compatible: must be "nxp,lpc3220-gpio" > -- reg: Physical base address and length of the controller's registers. > -- gpio-controller: Marks the device node as a GPIO controller. > -- #gpio-cells: Should be 3: > - 1) bank: > - 0: GPIO P0 > - 1: GPIO P1 > - 2: GPIO P2 > - 3: GPIO P3 > - 4: GPI P3 > - 5: GPO P3 > - 2) pin number > - 3) optional parameters: > - - bit 0 specifies polarity (0 for normal, 1 for inverted) > -- reg: Index of the GPIO group > - > -Example: > - > - gpio: gpio@40028000 { > - compatible = "nxp,lpc3220-gpio"; > - reg = <0x40028000 0x1000>; > - gpio-controller; > - #gpio-cells = <3>; /* bank, pin, flags */ > - }; > - > - leds { > - compatible = "gpio-leds"; > - > - led0 { > - gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ > - linux,default-trigger = "heartbeat"; > - default-state = "off"; > - }; > - > - led1 { > - gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ > - linux,default-trigger = "timer"; > - default-state = "off"; > - }; > - }; > diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml b/Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml > new file mode 100644 > index 000000000000..cea2f2bb2393 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/nxp,lpc3220-gpio.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/nxp,lpc3220-gpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP LPC3220 SoC GPIO controller > + > +maintainers: > + - Animesh Agarwal <animeshagarwal28@xxxxxxxxx> > + > +properties: > + compatible: > + const: nxp,lpc3220-gpio > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 3 > + description: | > + 1) bank: > + 0: GPIO P0 > + 1: GPIO P1 > + 2: GPIO P2 > + 3: GPIO P3 > + 4: GPI P3 > + 5: GPO P3 > + 2) pin number > + 3) flags: > + - bit 0 specifies polarity (0 for normal, 1 for inverted) > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/gpio/gpio.h> > + > + gpio@40028000 { > + compatible = "nxp,lpc3220-gpio"; > + reg = <0x40028000 0x1000>; > + gpio-controller; > + #gpio-cells = <3>; /* bank, pin, flags */ > + }; > -- > 2.45.2 >