On 18.06.2024 20:48, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`, > to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`. > > Previously, these bit masks were placed higher up in the bit range, which > did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these > masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any > conflicts. The updated masks are now: > - `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`) > - `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`) > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Tested-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index bfaeeb00ac4a..b79dd1ea2616 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -87,8 +87,8 @@ > PIN_CFG_FILNUM | \ > PIN_CFG_FILCLKSEL) > > -#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) > -#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) > +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54) > +#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46) > #define PIN_CFG_MASK GENMASK_ULL(31, 0) > > /*