Re: [PATCH V2 2/2] pinctrl: intel: fix bug of register offset calculation

[Mika Westerberg <mika.westerberg@xxxxxxxxx>]

On Wed, Nov 25, 2015 at 07:36:48PM +0800, Qipeng Zha wrote:
> The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS,
> GPI_IE, are not 24 for Broxton, Add a parameter to allow
> different platform to set correct value.
> 
> Signed-off-by: Qi Zheng <qi.zheng@xxxxxxxxx>
> Signed-off-by: Qipeng Zha <qipeng.zha@xxxxxxxxx>
> ---
>  drivers/pinctrl/intel/pinctrl-broxton.c      |  1 +
>  drivers/pinctrl/intel/pinctrl-intel.c        | 45 +++++++++++++++-------------
>  drivers/pinctrl/intel/pinctrl-intel.h        |  3 ++
>  drivers/pinctrl/intel/pinctrl-sunrisepoint.c |  1 +
>  4 files changed, 30 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
> index e42d5d4..5979d38 100644
> --- a/drivers/pinctrl/intel/pinctrl-broxton.c
> +++ b/drivers/pinctrl/intel/pinctrl-broxton.c
> @@ -28,6 +28,7 @@
>  		.padcfglock_offset = BXT_PADCFGLOCK,	\
>  		.hostown_offset = BXT_HOSTSW_OWN,	\
>  		.ie_offset = BXT_GPI_IE,		\
> +		.gpp_size = 32,                         \
>  		.pin_base = (s),			\
>  		.npins = ((e) - (s) + 1),		\
>  	}
> diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
> index e3f580b..8b88b60 100644
> --- a/drivers/pinctrl/intel/pinctrl-intel.c
> +++ b/drivers/pinctrl/intel/pinctrl-intel.c
> @@ -25,9 +25,6 @@
>  
>  #include "pinctrl-intel.h"
>  
> -/* Maximum number of pads in each group */
> -#define NPADS_IN_GPP			24
> -
>  /* Offset from regs */
>  #define PADBAR				0x00c
>  #define GPI_IS				0x100
> @@ -108,6 +105,7 @@ struct intel_pinctrl {
>  
>  #define gpiochip_to_pinctrl(c)	container_of(c, struct intel_pinctrl, chip)
>  #define pin_to_padno(c, p)	((p) - (c)->pin_base)
> +#define npads_in_gpp(c)		((c)->gpp_size)

This is pretty useless macro. You can just use community->gpp_size
everywhere. Up to you.

Acked-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>
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