Re: [PATCH 1/3] gpio: Add APM X-Gene SoC GPIO controller support

[Rob Herring <robherring2@xxxxxxxxx>]

On Wed, May 28, 2014 at 12:01 PM, Feng Kan <fkan@xxxxxxx> wrote:
> On Tue, May 27, 2014 at 9:59 AM, Feng Kan <fkan@xxxxxxx> wrote:
>> On Tue, May 27, 2014 at 1:25 AM, Linus Walleij <linus.walleij@xxxxxxxxxx> wrote:
>>> On Wed, May 21, 2014 at 1:54 AM, Feng Kan <fkan@xxxxxxx> wrote:
>>>
>>>> I see each bank as separate gpio chip. It is a simple way to
>>>> abstract the banks since they can operate independently.
>>>
>>> I think they should also be separate devices, and separate nodes
>>> in the device tree.
>>>
>>>> It also
>>>> provided me a way to fix the sysfs gpio base number, regardless if
>>>> a particular bank node is pulled out.
>>>
>>> The GPIO sysfs is unpredictable for this and many other
>>> reasons and should not be relied upon.
>>>
>>>> This is also done in similar way
>>>> in some other gpio drivers such as the dwapb gpio driver.
>>>
>>> I think the dwapb has it's registers mingled while your banks
>>> seem to be separate chunks.
>>
>> Thanks for the comments, I will fix these problems. Just some details
>> in terms of the register layout. I will break out the gpio to separate
>> device nodes as instructed, I will have to use the reg attribute to offset
>> bank registers. Please let me know if it is acceptable.
>>
>> gfc_gpio_fl0              GFC42'h1701c00c
>> gfc_gpio_fl0_mux      GFC42'h1701c010
>> gfc_gpio_fl1              GFC42'h1701c018
>> gfc_gpio_fl1_mux      GFC42'h1701c01c
>> gfc_gpio_fl2              GFC42'h1701c024
>> gfc_gpio_fl2_mux      GFC42'h1701c028
>> gfc_gpio_fl0_od        GFC42'h1701c030
>> gfc_gpio_fl1_od        GFC42'h1701c034
>> gfc_gpio_fl2_od        GFC42'h1701c038
>
> Please kindly give some guidance on this, as you can see the individual
> gpio bank is interleaved in the address space, it is not likely to break this
> into multiple device nodes.

It should be 1 node.

Rob
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