> + * The combined data structure is 8-byte aligned. So proper placement of this
> + * structure in the larger embedding data structure is needed to ensure that
> + * there is no hole in it.
On i386 u64 is only 4 bytes aligned. So you need to explicitely align
it to 8 bytes. Otherwise you risk the two members crossing a cache line, which
would be really expensive with atomics.
> + /*
> + * Code doesn't work if raw spinlock is larger than 4 bytes
> + * or is empty.
> + */
> + BUG_ON((sizeof(arch_spinlock_t) > 4) || (sizeof(arch_spinlock_t) == 0));
BUILD_BUG_ON
> +
> + spin_unlock_wait(plock); /* Wait until lock is released */
> + old.__lock_count = ACCESS_ONCE(*plockcnt);
> + get_lock = ((threshold >= 0) && (old.count == threshold));
> + if (likely(!get_lock && spin_can_lock(&old.lock))) {
What is that for? Why can't you do the CMPXCHG unconditially ?
If it's really needed, it is most likely a race?
The duplicated code should be likely an inline.
> +/*
> + * The presence of either one of the CONFIG_DEBUG_SPINLOCK or
> + * CONFIG_DEBUG_LOCK_ALLOC configuration parameter will force the
> + * spinlock_t structure to be 8-byte aligned.
> + *
> + * To support the spinlock/reference count combo data type for 64-bit SMP
> + * environment with spinlock debugging turned on, the reference count has
> + * to be integrated into the spinlock_t data structure in this special case.
> + * The spinlock_t data type will be 8 bytes larger if CONFIG_GENERIC_LOCKBREAK
> + * is also defined.
I would rather just disable the optimization when these CONFIGs are set
-Andi
--
ak@xxxxxxxxxxxxxxx -- Speaking for myself only.
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