On Mon, 2010-01-11 at 15:26 -0800, H. Peter Anvin wrote: > On 01/11/2010 12:17 PM, Pavel Machek wrote: > >> > >> Uhm, that's just plain wrong. > >> > >> It doesn't matter if there is a "special mapping layer" -- if you're > >> crossing multiple erase blocks you're still having more churn in > >> your flash translation layer, with more wear on the device, and > >> lower performance than if you didn't. > > > > Eraseblocks really should not matter. It is not as if each logical > > sector belongs to one eraseblock.... > > > > (OTOH, maybe the eraseblock *groups* that are basis for wear-leveling > > do, or maybe firmware is doing something really really strange.) > > Pavel > > Maybe they "should not" matter, but they *do* matter. In most existing > FTLs, each logical sector *does* belong to one erase block, although > which particular erase block that is of course moves around. However, > the invariant that matters though -- and the reason alignment matters -- > is that for most FTLs, the *offset* of any particular logical sector > within the erase block it currently belongs to is invariant, i.e. the > FTL operates on physical sectors which are the same size as the erase > blocks. I think the other reason why alignment matters, at least on eMMC, is that they most probably have several MLC NAND chips inside, and they use "striping". And what matters is whether your I/O request is aligned to the "striping I/O group" size or not. Yes, because the offsets are most probably invariant. -- Best Regards, Artem Bityutskiy (Артём Битюцкий) -- To unsubscribe from this list: send the line "unsubscribe linux-fsdevel" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
