> +/*
> + * If sqe->ext_cap is set to this for IORING_OP_READ/WRITE, then the SQE
> + * contains protection information, and ring needs to be setup with SQE128
> + */
> +#define EXT_CAP_PI (1U << 0)
> +
> +/* Second half of SQE128 for IORING_OP_READ/WRITE */
> +struct io_uring_sqe_ext {
> + /*
> + * Reserved space for extended capabilities that are added down the
> + * line. Kept in beginning to maintain contiguity with the free space
> + * in first SQE
> + */
> + __u64 rsvd0[4];
Thanks for documenting the design decision. But I still don't understand
it. Due to the layout it will be a bit hard to have fields spreading
form the "normal" SQE into the extended area anyway. Note that this
is not a rejection of the approach, but I don't understand the argument
for it.
> + /* only valid when EXT_CAP_PI is set */
> + __u16 flags;
> + __u16 pi_app_tag;
> + __u32 pi_len;
> + __u64 pi_addr;
> + __u64 pi_seed;
> + __u64 rsvd1;
.. but either way it would probably make sense to keep the reserved
areas together instead of spread out.
Otherwise this looks good to me.
