On Tue, Oct 19, 2021 at 05:40:13AM -1000, Linus Torvalds wrote: > On Tue, Oct 19, 2021 at 3:42 AM Andreas Gruenbacher <agruenba@xxxxxxxxxx> wrote: > > * Will Catalin Marinas's work for supporting arm64 sub-page faults > > be queued behind these patches? We have an overlap in > > fault_in_[pages_]readable fault_in_[pages_]writeable, so one of > > the two patch queues will need some adjustments. > > I think that on the whole they should be developed separately, I don't > think it's going to be a particularly difficult conflict. > > That whole discussion does mean that I suspect that we'll have to > change fault_in_iov_iter_writeable() to do the "every 16 bytes" or > whatever thing, and make it use an actual atomic "add zero" or > whatever rather than walk the page tables. But that's a conceptually > separate discussion from this one, I wouldn't actually want to mix up > the two issues too much. I agree we shouldn't mix the two at the moment. The MTE fix requires some more thinking and it's not 5.16 material yet. The atomic "add zero" trick isn't that simple for MTE since the arm64 atomic or exclusive instructions run with kernel privileges and therefore with the kernel tag checking mode. We could toggle the mode to match user's just for those atomic ops but it will make this probing even more expensive (though normally it's done on the slow path). The quick/backportable fix for MTE is probably to just disable tag checking on user addresses during pagefault_disabled(). As I mentioned in the other thread, a more elaborate fix I think is to change the uaccess routines to update an error code somewhere in a similar way to the arm64 __put_user_error(). But that would require changing lots of callers. -- Catalin
