On Thu, Jul 30, 2020 at 11:44:09PM +0300, Mike Rapoport wrote:
> On Thu, Jul 30, 2020 at 05:22:10PM +0100, Catalin Marinas wrote:
> > On Mon, Jul 27, 2020 at 07:29:31PM +0300, Mike Rapoport wrote:
> > > For instance, the following example will create an uncached mapping (error
> > > handling is omitted):
> > >
> > > fd = memfd_secret(SECRETMEM_UNCACHED);
> > > ftruncate(fd, MAP_SIZE);
> > > ptr = mmap(NULL, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
[...]
> > > +static int secretmem_mmap(struct file *file, struct vm_area_struct *vma)
> > > +{
> > > + struct secretmem_ctx *ctx = file->private_data;
> > > + unsigned long mode = ctx->mode;
> > > + unsigned long len = vma->vm_end - vma->vm_start;
> > > +
> > > + if (!mode)
> > > + return -EINVAL;
> > > +
> > > + if ((vma->vm_flags & (VM_SHARED | VM_MAYSHARE)) == 0)
> > > + return -EINVAL;
> > > +
> > > + if (mlock_future_check(vma->vm_mm, vma->vm_flags | VM_LOCKED, len))
> > > + return -EAGAIN;
> > > +
> > > + switch (mode) {
> > > + case SECRETMEM_UNCACHED:
> > > + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
> > > + fallthrough;
> > > + case SECRETMEM_EXCLUSIVE:
> > > + vma->vm_ops = &secretmem_vm_ops;
> > > + break;
> > > + default:
> > > + return -EINVAL;
> > > + }
> > > +
> > > + vma->vm_flags |= VM_LOCKED;
> > > +
> > > + return 0;
> > > +}
> >
> > I think the uncached mapping is not the right thing for arm/arm64. First
> > of all, pgprot_noncached() gives us Strongly Ordered (Device memory)
> > semantics together with not allowing unaligned accesses. I suspect the
> > semantics are different on x86.
>
> Hmm, on x86 it's also Strongly Ordered, but I didn't find any alignment
> restrictions. Is there a mode for arm64 that can provide similar
> semantics?
>
> Would it make sence to use something like
>
> #define pgprot_uncached(prot) \
> __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
> PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN)
>
> or is it too weak?
Reading Elena's email, that's about preventing speculative loads. While
the arm64 Normal NC is non-cacheable (equivalent to write-combine), a
CPU is allowed to speculatively read from it. A carefully crafted gadget
could leave an imprint on a different part of the cache via speculative
execution based on a value in the secret memory. So IIUC, we want memory
that cannot be speculatively loaded from and that would be Device memory
on arm64 (with the alignment restrictions).
Now, I think we could relax this to Device_GRE. So maybe add a
pgprot_nospec() and allow architectures to define whatever they find
suitable. The exact semantics will be different between architectures.
> > The second, more serious problem, is that I can't find any place where
> > the caches are flushed for the page mapped on fault. When a page is
> > allocated, assuming GFP_ZERO, only the caches are guaranteed to be
> > zeroed. Exposing this subsequently to user space as uncached would allow
> > the user to read stale data prior to zeroing. The arm64
> > set_direct_map_default_noflush() doesn't do any cache maintenance.
>
> Well, the idea of uncached mappings came from Elena [1] to prevent
> possibility of side channels that leak user space memory. So I think
> even without cache flushing after the allocation, user space is
> protected as all its memory accesses bypass cache so even after the page
> is freed there won't be stale data in the cache.
>
> I think that it makes sense to limit SECRETMEM_UNCACHED only for
> architectures that define an appropriate protection, e.g.
> pgprot_uncahced(). For x86 it can be aliased to pgprot_noncached() and
> other architecures can define their versions.
Indeed, though as I said above, maybe use a name that suggests no
speculation since non-cacheable doesn't always guarantee that. Something
like pgprot_nospec() and SECRETMEM_NOSPEC.
However, your implementation still has the problem that such memory must
have the caches flushed before being mapped in user-space, otherwise we
leak other secrets via such pages to the caller. The only generic API we
have in the kernel for such things is the DMA one. If hch doesn't mind,
you could abuse it and call arch_dma_prep_coherent() prior to
set_direct_map_invalid_noflush() (if the mapping is non-cacheable).
--
Catalin
