From: "Matthew Wilcox (Oracle)" <willy@xxxxxxxxxxxxx> This is the generic implementation. I can't figure out an optimised implementation for riscv. Signed-off-by: Matthew Wilcox (Oracle) <willy@xxxxxxxxxxxxx> Cc: Paul Walmsley <paul.walmsley@xxxxxxxxxx> Cc: Palmer Dabbelt <palmer@xxxxxxxxxxx> Cc: Albert Ou <aou@xxxxxxxxxxxxxxxxx> Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx --- arch/riscv/include/asm/bitops.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 396a3303c537..f2060c126a34 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -171,6 +171,13 @@ static inline void clear_bit_unlock( __op_bit_ord(and, __NOT, nr, addr, .rl); } +static inline bool clear_bit_unlock_is_negative_byte(unsigned int nr, + volatile unsigned long *p) +{ + clear_bit_unlock(nr, p); + return test_bit(7, p); +} + /** * __clear_bit_unlock - Clear a bit in memory, for unlock * @nr: the bit to set -- 2.25.1