On Sat, Sep 21, 2019 at 10:19 AM Al Viro <viro@xxxxxxxxxxxxxxxxxx> wrote:
>
> BTW, how much is the cost of smp_store_release() affected by a recent
> smp_store_release() on the same CPU?
Depends on the architecture.
On x86, smp_store_release() is free - all stores are releases.
(Well, there's the cost of the compiler barrier and the fact that gcc
generates horrid code for volatiles, but that's it).
On modern arm64 it should be fairly cheap. A store-release is just
about the cheapest barrier you can find.
On ppc, it's an lwsync, which is again the cheapest barrier there is,
and is usually just a few cycles. Although on older powerpc I think it
becomes a 'sync' which is fairly expensive.
Other architectures are a mix of the above. It's usually not all that
expensive, but ..
> IOW, if we have
> smp_store_release(p, v1);
> <some assignments into the same cacheline>
> r = *q; // different cacheline
> smp_store_release(q, v2);
> how much overhead will the second smp_store_release() give?
It really should only order the store queue, and make sure that
earlier reads have completed by the time the store queue entry drains.
Which sounds like a big deal, but since you have to be all kinds of
silly to delay reads past later writes (reads are latency-important,
buffered writes are not), that really isn't a performance issue.
Except some architectures are stupid and lack the proper barrier
model, and then it can be a full memory barrier. But honestly, I don't
think we have any architecture where we really care.
Linus
