Will Deacon <will@xxxxxxxxxx> wrote:
> > + /* Barrier: head belongs to the write side, so order reading
> > + * the data after reading the head pointer.
> > + */
> > + unsigned int head = READ_ONCE(pipe->head);
>
> Hmm, I don't understand this. Since READ_ONCE() doesn't imply a barrier,
> how are you enforcing the read-read ordering in the CPU?
It does imply a barrier: smp_read_barrier_depends(). I believe that's
> What is the purpose of saying "This may need to insert a barrier"? Can this
> function be overridden or something?
I mean it's arch-dependent whether READ_ONCE() inserts a barrier or not.
> Saying that "This inserts a barrier" feels misleading, because READ_ONCE()
> doesn't do that.
Yes it does - on the Alpha:
[arch/alpha/include/asm/barrier.h]
#define read_barrier_depends() __asm__ __volatile__("mb": : :"memory")
[include/asm-generic/barrier.h]
#ifndef __smp_read_barrier_depends
#define __smp_read_barrier_depends() read_barrier_depends()
#endif
...
#ifndef smp_read_barrier_depends
#define smp_read_barrier_depends() __smp_read_barrier_depends()
#endif
[include/linux/compiler.h]
#define __READ_ONCE(x, check) \
({ \
union { typeof(x) __val; char __c[1]; } __u; \
if (check) \
__read_once_size(&(x), __u.__c, sizeof(x)); \
else \
__read_once_size_nocheck(&(x), __u.__c, sizeof(x)); \
smp_read_barrier_depends(); /* Enforce dependency ordering from x */ \
__u.__val; \
})
#define READ_ONCE(x) __READ_ONCE(x, 1)
See:
commit 76ebbe78f7390aee075a7f3768af197ded1bdfbb
Author: Will Deacon <will.deacon@xxxxxxx>
Date: Tue Oct 24 11:22:47 2017 +0100
locking/barriers: Add implicit smp_read_barrier_depends() to READ_ONCE()
David
