From: Fabio Estevam <festevam@xxxxxxx> Convert the Altera Passive Serial SPI FPGA Manager binding from text file to yaml format to allow devicetree validation. Signed-off-by: Fabio Estevam <festevam@xxxxxxx> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- .../bindings/fpga/altera-passive-serial.txt | 29 -------- .../fpga/altr,fpga-passive-serial.yaml | 74 +++++++++++++++++++ 2 files changed, 74 insertions(+), 29 deletions(-) delete mode 100644 Documentation/devicetree/bindings/fpga/altera-passive-serial.txt create mode 100644 Documentation/devicetree/bindings/fpga/altr,fpga-passive-serial.yaml diff --git a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt b/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt deleted file mode 100644 index 48478bc07e29..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-passive-serial.txt +++ /dev/null @@ -1,29 +0,0 @@ -Altera Passive Serial SPI FPGA Manager - -Altera FPGAs support a method of loading the bitstream over what is -referred to as "passive serial". -The passive serial link is not technically SPI, and might require extra -circuits in order to play nicely with other SPI slaves on the same bus. - -See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf - -Required properties: -- compatible: Must be one of the following: - "altr,fpga-passive-serial", - "altr,fpga-arria10-passive-serial" -- reg: SPI chip select of the FPGA -- nconfig-gpios: config pin (referred to as nCONFIG in the manual) -- nstat-gpios: status pin (referred to as nSTATUS in the manual) - -Optional properties: -- confd-gpios: confd pin (referred to as CONF_DONE in the manual) - -Example: - fpga: fpga@0 { - compatible = "altr,fpga-passive-serial"; - spi-max-frequency = <20000000>; - reg = <0>; - nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; - confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altr,fpga-passive-serial.yaml b/Documentation/devicetree/bindings/fpga/altr,fpga-passive-serial.yaml new file mode 100644 index 000000000000..ffb7cc54556f --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altr,fpga-passive-serial.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/altr,fpga-passive-serial.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Passive Serial SPI FPGA Manager + +maintainers: + - Fabio Estevam <festevam@xxxxxxx> + +description: | + Altera FPGAs support a method of loading the bitstream over what is + referred to as "passive serial". + The passive serial link is not technically SPI, and might require extra + circuits in order to play nicely with other SPI slaves on the same bus. + + See https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - altr,fpga-passive-serial + - altr,fpga-arria10-passive-serial + + spi-max-frequency: + maximum: 20000000 + + reg: + maxItems: 1 + + nconfig-gpios: + description: + Config pin (referred to as nCONFIG in the manual). + maxItems: 1 + + nstat-gpios: + description: + Status pin (referred to as nSTATUS in the manual). + maxItems: 1 + + confd-gpios: + description: + confd pin (referred to as CONF_DONE in the manual) + maxItems: 1 + +required: + - compatible + - reg + - nconfig-gpios + - nstat-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + fpga@0 { + compatible = "altr,fpga-passive-serial"; + reg = <0>; + nconfig-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + nstat-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + confd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + }; + }; +... -- 2.34.1
