From: Ian Dannapel <iansdannapel@xxxxxxxxx> Add device tree binding documentation for configuring Efinix FPGA using serial SPI passive programming mode. Signed-off-by: Ian Dannapel <iansdannapel@xxxxxxxxx> --- .../fpga/efinix,trion-spi-passive.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml new file mode 100644 index 000000000000..ec6697fa6f44 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-spi-passive.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-spi-passive.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel <iansdannapel@xxxxxxxxx> + +description: | + Efinix Trion and Titanium Series FPGAs support a method of loading the + bitstream over what is referred to as "SPI Passive Programming". + Only serial (1x bus width) is supported, setting the programming mode + is not in the scope the this manager and must be done elsewhere. + + Warning: The slave serial link is not technically SPI and therefore it is + not recommended to have other devices on the same bus since it might + interfere or be interfered by other transmissions. + + References: + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.6.pdf + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.0.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - efinix,trion-spi-passive + - efinix,titanium-spi-passive + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + creset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cs-gpios: + description: + chip-select pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - creset-gpios + - cs-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + fpga-mgr@0 { + compatible = "efinix,trion-spi-passive"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + creset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +... -- 2.34.1
