----- On Feb 1, 2024, at 3:07 AM, Krzysztof Kozlowski krzysztof.kozlowski@xxxxxxxxxx wrote: > On 01/02/2024 00:05, Charles Perry wrote: >> Document the slave SelectMAP interface of Xilinx 7 series FPGA. >> >> Signed-off-by: Charles Perry <charles.perry@xxxxxxxxxxxxxxxxxxxx> >> --- >> .../bindings/fpga/xlnx,fpga-selectmap.yaml | 83 +++++++++++++++++++ >> 1 file changed, 83 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> >> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> new file mode 100644 >> index 0000000000000..c9a446b43cdd9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-selectmap.yaml >> @@ -0,0 +1,83 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx SelectMAP FPGA interface >> + >> +maintainers: >> + - Charles Perry <charles.perry@xxxxxxxxxxxxxxxxxxxx> >> + >> +description: | >> + Xilinx 7 Series FPGAs support a method of loading the bitstream over a >> + parallel port named the SelectMAP interface in the documentation. Only >> + the x8 mode is supported where data is loaded at one byte per rising edge of >> + the clock, with the MSB of each byte presented to the D0 pin. >> + >> + Datasheets: >> + >> https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf >> + >> +allOf: >> + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# >> + >> +properties: >> + compatible: >> + enum: >> + - xlnx,fpga-selectmap > > Your description mentions "7 Series" which is not present in compatible > and title. What is exactly the product here? Interface usually is not > the final binding, so is this specific to some particular FPGA or SoC? > > > Best regards, > Krzysztof This is specific to the FPGA, the 7 series encompass the following part family: * Spartan-7 (XC7S6, XC7S15, ... XC7S100) * Artix-7 (XC7A12T, XC7A15T, ... XC7A200T) * Kintex-7 (XC7K70T, XC7K160T, ... XC7K480T) * Virtex-7 (XC7V585T, XC7V2000T, XC7VX330T, XC7VX415T, ... XC7VX1140T, XC7VH580T, XC7VH870T) The configuration guide of Xilinx [1] tells us that all those devices share a common programming scheme. I do agree that having a mention of "7 series" in the compatible name would be beneficial as Xilinx has more FPGA than just the 7 series. The name was inspired from "xlnx,fpga-slave-serial" which is the compatible for the serial interface. What about "xlnx,fpga-xc7-selectmap" ? I'm also seeing that I missed some mention of the "slave" word in the commit message, will fix. Regards, Charles [1] https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
