Document the slave SelectMAP interface of Xilinx 7 series FPGA. Signed-off-by: Charles Perry <charles.perry@xxxxxxxxxxxxxxxxxxxx> --- .../fpga/xlnx,fpga-slave-selectmap.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml diff --git a/Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml b/Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml new file mode 100644 index 0000000000000..20cea24e3e39a --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xlnx,fpga-slave-selectmap.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-selectmap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Slave SelectMAP FPGA + +description: | + Xilinx 7 Series FPGAs support a method of loading the bitstream over a + parallel port named the slave SelectMAP interface in the documentation. Only + the x8 mode is supported where data is loaded at one byte per rising edge of + the clock, with the MSB of each byte presented to the D0 pin. + + Datasheets: + https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf + +properties: + compatible: + enum: + - xlnx,fpga-slave-selectmap + + reg: + description: + At least 1 byte of memory mapped IO + maxItems: 1 + + prog_b-gpios: + description: + config pin (referred to as PROGRAM_B in the manual) + maxItems: 1 + + done-gpios: + description: + config status pin (referred to as DONE in the manual) + maxItems: 1 + + init-b-gpios: + description: + initialization status and configuration error pin + (referred to as INIT_B in the manual) + maxItems: 1 + + csi-b-gpios: + description: + chip select pin (referred to as CSI_B in the manual) + Optional gpio for if the bus controller does not provide a chip select. + maxItems: 1 + + rdwr-b-gpios: + description: + read/write select pin (referred to as RDWR_B in the manual) + Optional gpio for if the bus controller does not provide this pin. + maxItems: 1 + +required: + - compatible + - reg + - prog_b-gpios + - done-gpios + - init-b-gpios + +additionalProperties: true + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + &weim { + status = "okay"; + ranges = <0 0 0x08000000 0x04000000>; + + fpga_mgr: fpga_programmer@0,0 { + compatible = "xlnx,fpga-slave-selectmap"; + reg = <0 0 0x4000000>; + fsl,weim-cs-timing = <0x00070031 0x00000142 + 0x00020000 0x00000000 + 0x0c000645 0x00000000>; + prog_b-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + init-b-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + done-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + csi-b-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; + rdwr-b-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + }; +... -- 2.43.0
