From: Alfonso Rodriguez <alfonso.rodriguezm@xxxxxx> The Zynq platform has PCAP, ICAP and JTAG interfaces for configuring programmable logic (PL). The existing driver implementation uses the PCAP interface to configure the PL. Before switching the PL configuration interface from PCAP to ICAP make sure that all outstanding Transactions relevant to the PL configuration should be completed by the PCAP interface otherwise it may lead to PL configuration issues. This patch provides a required fix to ensure that all existing PL transactions are completed before switching from PCAP to ICAP. For detailed information relevant to PL configuration interfaces refer Zynq 7000 TRM (section 6.5.1). Link: https://docs.xilinx.com/v/u/en-US/ug585-Zynq-7000-TRM Signed-off-by: Alfonso Rodriguez <alfonso.rodriguezm@xxxxxx> Signed-off-by: Nava kishore Manne <nava.kishore.manne@xxxxxxx> --- Changes for v3: - Fixed some minor code alignment issues. Changes for v2: - Updated commit message and added Doc link as suggested by Yilun. drivers/fpga/zynq-fpga.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c index ae0da361e6c6..f8214cae9b6e 100644 --- a/drivers/fpga/zynq-fpga.c +++ b/drivers/fpga/zynq-fpga.c @@ -493,15 +493,15 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, if (err) return err; - /* Release 'PR' control back to the ICAP */ - zynq_fpga_write(priv, CTRL_OFFSET, - zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); - err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, intr_status & IXR_PCFG_DONE_MASK, INIT_POLL_DELAY, INIT_POLL_TIMEOUT); + /* Release 'PR' control back to the ICAP */ + zynq_fpga_write(priv, CTRL_OFFSET, + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK); + clk_disable(priv->clk); if (err) -- 2.25.1
