On 2023-04-17 at 12:26:51 +0300, Ilpo Järvinen wrote:
> Wrap regmap_update_bits() with m10bmc_sys_update_bits() in order to be
> able to add additional checks into it.
>
> Co-developed-by: Russ Weight <russell.h.weight@xxxxxxxxx>
> Signed-off-by: Russ Weight <russell.h.weight@xxxxxxxxx>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
Acked-by: Xu Yilun <yilun.xu@xxxxxxxxx>
> ---
> drivers/fpga/intel-m10-bmc-sec-update.c | 30 ++++++++++++-------------
> drivers/mfd/intel-m10-bmc-core.c | 9 ++++++++
> include/linux/mfd/intel-m10-bmc.h | 4 ++++
> 3 files changed, 27 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/fpga/intel-m10-bmc-sec-update.c b/drivers/fpga/intel-m10-bmc-sec-update.c
> index d7e2f9f461bc..fe0127a58eff 100644
> --- a/drivers/fpga/intel-m10-bmc-sec-update.c
> +++ b/drivers/fpga/intel-m10-bmc-sec-update.c
> @@ -376,12 +376,11 @@ static enum fw_upload_err rsu_update_init(struct m10bmc_sec *sec)
> u32 doorbell_reg, progress, status;
> int ret, err;
>
> - ret = regmap_update_bits(sec->m10bmc->regmap,
> - csr_map->base + csr_map->doorbell,
> - DRBL_RSU_REQUEST | DRBL_HOST_STATUS,
> - DRBL_RSU_REQUEST |
> - FIELD_PREP(DRBL_HOST_STATUS,
> - HOST_STATUS_IDLE));
> + ret = m10bmc_sys_update_bits(sec->m10bmc, csr_map->doorbell,
> + DRBL_RSU_REQUEST | DRBL_HOST_STATUS,
> + DRBL_RSU_REQUEST |
> + FIELD_PREP(DRBL_HOST_STATUS,
> + HOST_STATUS_IDLE));
> if (ret)
> return FW_UPLOAD_ERR_RW_ERROR;
>
> @@ -450,11 +449,10 @@ static enum fw_upload_err rsu_send_data(struct m10bmc_sec *sec)
> u32 doorbell_reg, status;
> int ret;
>
> - ret = regmap_update_bits(sec->m10bmc->regmap,
> - csr_map->base + csr_map->doorbell,
> - DRBL_HOST_STATUS,
> - FIELD_PREP(DRBL_HOST_STATUS,
> - HOST_STATUS_WRITE_DONE));
> + ret = m10bmc_sys_update_bits(sec->m10bmc, csr_map->doorbell,
> + DRBL_HOST_STATUS,
> + FIELD_PREP(DRBL_HOST_STATUS,
> + HOST_STATUS_WRITE_DONE));
> if (ret)
> return FW_UPLOAD_ERR_RW_ERROR;
>
> @@ -517,11 +515,10 @@ static enum fw_upload_err rsu_cancel(struct m10bmc_sec *sec)
> if (rsu_prog(doorbell) != RSU_PROG_READY)
> return FW_UPLOAD_ERR_BUSY;
>
> - ret = regmap_update_bits(sec->m10bmc->regmap,
> - csr_map->base + csr_map->doorbell,
> - DRBL_HOST_STATUS,
> - FIELD_PREP(DRBL_HOST_STATUS,
> - HOST_STATUS_ABORT_RSU));
> + ret = m10bmc_sys_update_bits(sec->m10bmc, csr_map->doorbell,
> + DRBL_HOST_STATUS,
> + FIELD_PREP(DRBL_HOST_STATUS,
> + HOST_STATUS_ABORT_RSU));
> if (ret)
> return FW_UPLOAD_ERR_RW_ERROR;
>
> @@ -764,3 +761,4 @@ module_platform_driver(intel_m10bmc_sec_driver);
> MODULE_AUTHOR("Intel Corporation");
> MODULE_DESCRIPTION("Intel MAX10 BMC Secure Update");
> MODULE_LICENSE("GPL");
> +MODULE_IMPORT_NS(INTEL_M10_BMC_CORE);
> diff --git a/drivers/mfd/intel-m10-bmc-core.c b/drivers/mfd/intel-m10-bmc-core.c
> index c0b8209fd842..dab1bb152fd6 100644
> --- a/drivers/mfd/intel-m10-bmc-core.c
> +++ b/drivers/mfd/intel-m10-bmc-core.c
> @@ -12,6 +12,15 @@
> #include <linux/mfd/intel-m10-bmc.h>
> #include <linux/module.h>
>
> +int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,
> + unsigned int msk, unsigned int val)
> +{
> + const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map;
> +
> + return regmap_update_bits(m10bmc->regmap, csr_map->base + offset, msk, val);
> +}
> +EXPORT_SYMBOL_NS_GPL(m10bmc_sys_update_bits, INTEL_M10_BMC_CORE);
> +
> static ssize_t bmc_version_show(struct device *dev,
> struct device_attribute *attr, char *buf)
> {
> diff --git a/include/linux/mfd/intel-m10-bmc.h b/include/linux/mfd/intel-m10-bmc.h
> index 1812ebfa11a8..5418f7279ed0 100644
> --- a/include/linux/mfd/intel-m10-bmc.h
> +++ b/include/linux/mfd/intel-m10-bmc.h
> @@ -251,6 +251,7 @@ struct intel_m10bmc {
> *
> * m10bmc_raw_read - read m10bmc register per addr
> * m10bmc_sys_read - read m10bmc system register per offset
> + * m10bmc_sys_update_bits - update m10bmc system register per offset
> */
> static inline int
> m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
> @@ -282,6 +283,9 @@ static inline int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offs
> return m10bmc_raw_read(m10bmc, csr_map->base + offset, val);
> }
>
> +int m10bmc_sys_update_bits(struct intel_m10bmc *m10bmc, unsigned int offset,
> + unsigned int msk, unsigned int val);
> +
> /*
> * MAX10 BMC Core support
> */
> --
> 2.30.2
>
